搜索资源列表
CPLD
- 基于CPLD的高速AD采样的VHDL程序-Based on CPLD high-speed AD sampling VHDL program
adconfig
- 一般AD模数转换器的VHDL配置程序，输出为14位串口输出，状态机实现的。-General AD ADC VHDL configuration program, the output is 14 serial output, the state machine implementation.
daconfig
- 一般DA模数转换器的VHDL配置程序，输入为14位串口输出，状态机实现的。-General AD ADC VHDL configuration program, the output is 14 serial output, the state machine implementation.
ADC_DAC_V2.0_EP2C35Q240C8
- 基于vhdl的AD DA 高速转换，EP3C25Q240-Based vhdl of AD DA conversion speed, EP3C25Q240
ADC0809-
- ADC0809 AD转换器的VHDL程序实现-ADC0809 AD converter VHDL program realization
ADVHDL
- 用fpga控制ad采集，用vhdl编写，可控制采样率-With fpga control ad acquisition, with vhdl written to control the sampling rate
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
AD7895
- 读取AD7895 的12位ADC转换值，连续读取方式，采样速率为20mS 一次。(Read the 12 bit ADC conversion value of AD7895.)